1. Field of the Invention
This invention is related to the field of computer systems and processors, and more particularly to I/O remapping mechanisms in computer systems and processors.
2. Description of the Related Art
Generally, computer systems include one or more processors (also referred to in some cases as central processing units, or CPUs), memory (e.g. dynamic random access memory (DRAM), synchronous DRAM (SDRAM), RAMBUS DRAM (RDRAM), etc.), and one or more peripheral devices connected to one or more peripheral buses. Typically, the processors communicate with the peripheral devices through various registers (e.g. configuration and control registers in the peripheral device) for configuration and for relatively small amounts of data communication (e.g. control messages). These registers are often memory-mapped (i.e. assigned addresses in the memory map of the processor). Also, processors communicate with the peripheral devices for larger amounts of data using direct memory access (or DMA), in which a given peripheral device is provided with a memory address to directly transfer data to or from the memory locations at the memory address).
The amount of memory in many types of computer systems has often been less than 4 gigabytes (GB) (the amount of memory addressable with 32 bits of address). For example, the memory in personal computer (PC) systems and in many server computer systems has generally been less than 4 GB. In part, cost/performance tradeoffs have lead to such computer systems having less than 4 GB of memory.
Most peripheral devices are capable of generating 32 bit addresses. For example, many peripheral devices are designed for the Peripheral Component Interconnect (PCI) bus, which includes a 32 bit address. Accordingly, peripheral devices may DMA to any memory address and thus read/write any of the memory included in a computer system having less than 4 GB of memory.
The memory included in computer systems has been increasing, as has the memory addressing capability of many processors. Some processor architectures have included greater than 32 bits of addressing (e.g. up to 64 bits) for some time (e.g. the Alpha processor architecture, the Sparc processor architecture, or the PowerPC processor architecture). The x86 processor architecture (also referred to as IA-32) has had provisions for 36 bits of physical address (although virtual addresses were still limited to 32 bits) for some time as well. Recently, Advanced Micro Devices, Inc. announced an extension to the x86 processor architecture to allow for greater than 32 bits of addressing (e.g. up to 64 bits). Accordingly, more and more processors are capable of greater than 32 bits of addressing. Additionally, as the memory demands of the operating systems and application programs being used in computer systems increase, the amount of memory in computer systems has been increasing to satisfy the memory demands. Computer systems including greater than 4 GB of memory are thus expected to be more common.
While computer systems are expected to more frequently include more than 4 GB of memory, some peripheral devices are expected to be capable of addressing a maximum of 4 GB of memory. Such devices will not be able to directly address the memory at addresses above 4 GB. However, an operating system routine or application program may be allocated memory above the 4 GB limit, and may wish a peripheral device to DMA data to or from that memory.
Some computer systems may handle the above situation by copying the data to/from another block of memory below the 4 GB limit. For example, for a DMA write to memory, the DMA may be performed to a block of memory below the 4 GB limit and the data may be copied to the memory allocated to the receiving application program or operating system routine (above the 4 GB limit). For a DMA read from memory, the data to be read may be copied to a block of memory below the 4 GB limit and the DMA may be performed from that memory location. Additionally, some computer systems have included specific hardware (i.e. a separate chipset component) to use a separate I/O remapping table to remap peripheral addresses below the 4 GB limit to addresses above the 4 GB limit.